Semiconductor device

ABSTRACT

A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/487,762 filed Sep. 16, 2014 which is claiming priority from JapanesePatent Application No. 2013-198300 filed on Sep. 25, 2013 including thespecification, drawings and abstract is incorporated herein by referencein its entirety.

BACKGROUND

The present invention relates to a semiconductor device and is atechnology applicable, for example, to a semiconductor device in whichtwo semiconductor chips are layered.

Among the semiconductor devices, there is a device in which twosemiconductor chips of a first semiconductor chip and a secondsemiconductor chip are layered with element formation planes thereofmade to face mutually (for example, Japanese Unexamined PatentApplication Publication No. 2011-54800). A technology described inJapanese Unexamined Patent Application Publication No. 2011-54800 is onethat makes the first semiconductor chip and the second semiconductorchip transmit and receive a signal therebetween. Specifically, aninductor is formed in each of the first semiconductor chip and thesecond semiconductor chip, and these inductors are faced mutually. Then,transmission and reception of the signal is performed between the firstsemiconductor chip and the second semiconductor chip by transmitting andreceiving the signal between these inductors.

Moreover, Japanese Unexamined Patent Application Publication. No.2011-54800 describes a semiconductor device in which the firstsemiconductor chip is mounted over an element mounting part of a leadframe, and further the second semiconductor chip is mounted over thisfirst semiconductor chip. In this semiconductor device, a part of anelement formation plane of the second semiconductor chip protrudes fromthe first semiconductor chip. Then, the second semiconductor chip and alead terminal are coupled by using a bonding wire.

SUMMARY

The present inventors have examined a method whereby a firstsemiconductor chip is mounted over an element mounting part of a leadframe, a second semiconductor chip is mounted over this firstsemiconductor chip with its element formation plane faced to the firstsemiconductor chip, and further the second semiconductor chip and a leadterminal are coupled each other with a bonding wire. In this case, whenthe semiconductor device is miniaturized, as a result of the presentinventors' examination, it has been considered that there comes out apossibility that a bonding head for coupling a bonding wire to thesecond semiconductor chip will interfere with the element mounting part.Other problems and new features will become clear from description andaccompanying drawings of this specification.

According to one embodiment, the semiconductor device has a chipmounting part, a first semiconductor chip, and a second semiconductorchip. The first semiconductor chip is mounted over the chip mountingpart in a direction in which its first principal plane faces the chipmounting part. A part of the second semiconductor chip is mounted overthe first semiconductor chip in a direction in which its third principalplane faces the first semiconductor chip. The element mounting part hasa notch part. A part of the second semiconductor chip overlaps the notchpart. A second electrode pad is provided in a region of the thirdprincipal plane of the second semiconductor chip that overlaps the notchpart. A first bonding wire couples to a first electrode pad of the firstsemiconductor chip, and a second bonding wire couples to the secondelectrode pad.

According to the one embodiment, it is possible to suppress a bondinghead for coupling the bonding wire to the second semiconductor chip frominterfering with the element mounting part.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plane view showing a configuration of semiconductor deviceaccording to an embodiment;

FIG. 2 is an A-A′ sectional view of FIG. 1;

FIG. 3 is a diagram enlarging a region surrounded by dotted line of FIG.1;

FIG. 4 is a diagram enlarging a region enclosed with a dotted line ofFIG. 2;

FIG. 5 is a plane view showing one example of a structure of a firstsemiconductor chip;

FIG. 6 is a B-B′ sectional view of FIG. 5;

FIG. 7 is a plane view showing one example of a structure of a secondsemiconductor chip;

FIG. 8, is a C-C′ sectional view of FIG. 7;

FIG. 9 is a sectional view showing a first example of a shape of a fixedlayer;

FIG. 10 is a sectional view showing a second example of the shape of thefixed layer;

FIG. 11 is a sectional view showing a third example of the shape of thefixed layer;

FIGS. 12A and 12B are sectional, views for explaining a method formanufacturing a semiconductor device;

FIGS. 13A and 13B are sectional views for explaining the method formanufacturing a semiconductor device;

FIGS. 14A, 14B, and 14C are sectional views for explaining a method formanufacturing a semiconductor device;

FIGS. 15A, 158, and 15C are sectional views for explaining the methodfor manufacturing a semiconductor device;

FIGS. 16A and 16B are flowcharts showing details of steps shown in FIGS.13A and 13B;

FIGS. 17A and 17B are flowcharts showing details of steps shown in FIGS.13A and 13B;

FIG. 18 is a plane view of a first, semiconductor chip according to amodification; and

FIG. 19 is a plane view of a second semiconductor chip according to themodification.

DETAILED DESCRIPTION

Hereinafter, embodiments will be explained using drawings. Incidentally,in all the drawings, the same sign is given to the same component andits explanation is omitted suitably.

Embodiment

FIG. 1 is a plane view showing a configuration of semiconductor deviceSD according to an embodiment. FIG. 2 is an A-A′ sectional view ofFIG. 1. FIG. 3 is a diagram enlarging a region enclosed with a dottedline of FIG. 1. FIG. 4 is a diagram enlarging a region enclosed with adotted line of FIG. 2. The semiconductor device SD according to theembodiment has a chip mounting part DP, a first semiconductor chip SC1,and a second semiconductor chip SC2. The first semiconductor chip SC1 ismounted over the chip mounting part DP; a part of the secondsemiconductor chip SC2 is mounted over the first semiconductor chip SC1.

In detail, as shown in FIG. 2, the first semiconductor chip SC1 has afirst principal plane SFC1 and a second principal plane SFC2. The secondprincipal plane SFC2 is a plane opposite to the first principal planeSFC1. The first semiconductor chip SC1 is mounted over the chip mountingpart DP in a direction in which the second principal plane SFC2 facesthe chip mounting part DP.

Moreover, as shown in FIG. 2, the second semiconductor chip SC2 has athird principal plane SFC3 and a fourth principal plane SFC4. The fourthprincipal plane SFC4 is a plane opposite to the third principal planeSFC3. Then, the part of the second semiconductor chip SC2 is mountedover the first semiconductor chip SC1 in a direction in which the thirdprincipal plane SFC3 faces the first principal plane SFC1.

As shown in FIG. 1 and FIG. 3, in plane view, the chip mounting part DPhas a notch part CP. A part of the second semiconductor chip SC2overlaps the notch part CP. Moreover, in a portion of the firstprincipal plane SFC1 of the first semiconductor chip SC1 that does notoverlap the second semiconductor chip SC2, first electrode pads PAD11,PAD12 are provided; in a region of the third principal plane SFC3 of thesecond semiconductor chip SC2 that does not overlap the notch part CP, asecond electrode, pad PAD2 is provided. In addition, the semiconductordevice SD has a first bonding wire WIR1 and a second bonding wire WIR2.One end of the first bonding wire WIR1 is coupled to the first electrodepad PAD11 (or the first electrode pad PAD12); one end of the secondbonding wire WIR2 is coupled to the second electrode pad PAD2. In thefollowing, they will be explained in detail.

The first semiconductor chip SC1 is, for example, a semiconductor chipfor power control and has a power transistor for power control and acontrol circuit for controlling this power transistor. Further, thefirst semiconductor chip SC1 may have a logic circuit. The secondsemiconductor chip SC2 is, for example, a microcomputer (amicrocontroller (MCU: Micro Control. Unit), a microprocessor (MPU:Micro-Processing Unit)), or the like. Then, the first semiconductor chipSC1 is larger in size than the second semiconductor chip SC2. In thiscase, as shown in this embodiment, a structure of the semiconductordevice SD is stabilized by locating the first semiconductor chip SC1under the second semiconductor chip SC2. However, the firstsemiconductor chip SC1 may have a size of the same order as that of thesecond semiconductor chip SC2.

Moreover, the second semiconductor chip SC2 is made thicker than thefirst semiconductor chip SC1. For example, the thickness of the firstsemiconductor chip SC1 is not less than 100 μm and not more than 300 μm;the thickness of the second semiconductor chip SC2 is not less than 300μm and not more than 500 μm.

In an example shown in FIG. 1 and FIG. 2, the chip mounting part DP is adie pad of a lead frame, and is an approximately polygon, for example, arectangle. Then, the notch part CP is provided on a side SID1 of thechip mounting part DP. Designating a length of the second semiconductorchip SC2 both in plane view and in a direction perpendicular to the sideSID1 as L (refer to FIGS. 1 and 3), a distance e from an end of aportion of the second semiconductor chip SC2 that is located on thefirst semiconductor chip SC1 to the notch part CP is set to more than orequal to L/2 (refer to FIGS. 1 and 3). In the example shown in FIG. 1,the chip mounting part DP is an approximately rectangle and the sideSID1 is a long side of the chip mounting part DP. Then, one end of asupport part FS1 (for example, a suspension lead) couples to each of twosides that intersect the side SID1 among three remaining sides of thechip mounting part DP. In the example shown in FIG. 1, the support partFS1 is coupled to almost a center of a short side of the chip mountingpart DP.

Moreover, a support part FS2 is also coupled to the chip mounting partDP. The support part FS2 is also the suspension lead, and is locatedbetween lead terminals of the lead frame. In other words, the supportpart FS2 is such that a terminal being coupled to neither the firstsemiconductor chip SC1 nor the second semiconductor chip SC2 among thelead terminals is made to be the suspension lead. For this reason, anend of the support part FS2 that is not coupled to the chip mountingpart DP extends to the outside of a sealing resin MDR (to be describedlater). By the support part FS2 being provided, a position and adirection of the chip mounting part DP are stabilized. Moreover, sincethe lead terminal is diverted as the support part FS2, it is possible tosuppress the lead frame from enlarging as compared with the case ofadding newly the suspension lead.

In the example shown in FIG. 1, multiple second lead terminals LT2 areprovided on a side of the chip mounting part DP that faces the sideSID1. Then, in plane view, multiple first lead terminals LT1 areprovided on the opposite side of the second lead terminals LT2 acrossthe chip mounting part DP. The other end of the second bonding wire.WIR2 couples to the second lead terminal LT2, and the other end of thefirst bonding wire WIR1 couples to the first lead terminal LT1. Then,the support part FS2 is provided among the multiple first lead terminalsLT1. Specifically, two support parts FS2 are provided. The two supportparts FS2 are coupled to two angles that are not linked to the side SID1among four angles of the chip mounting part DP, respectively.Incidentally, ends of the first lead terminals LT1 that are coupled tothe first bonding wires WIR1 face the short side of the chip mountingpart DP.

Moreover, a plane of the first lead terminal LT1 to which the firstbonding wire WIR1 is coupled (in an example shown in FIG. 2, a planeopposite to the first principal plane SFC1 of the first semiconductorchip SC1) and a plane of the second lead terminal LT1 to which thesecond bonding wire WIR2 is coupled (in the example shown in FIG. 2, aplane opposite to the third principal plane SFC3 of the secondsemiconductor chip SC2) are opposite mutually. Then, a metal layer ML1is formed over a plane of a wire coupling side end of the first leadterminal LT1 to which the first bonding wire WIR1 is coupled; a metallayer ML2 is formed over a plane of a wire coupling side end of thesecond lead terminal LT2 to which the second bonding wire WIR2 iscoupled. In other words, a plane of the second lead terminal LT2 overwhich the metal layer ML2 is formed is opposite to a plane of the firstlead terminal LT1 over which the metal layer ML1 is formed. The metallayers ML1, ML2 are formed with a metal that easily join the bondingwire. In the case where the bonding wire is a gold wire, the metallayers ML1, ML2 are formed, for example, of tin silver plating or thelike.

Incidentally, since the first semiconductor chip SC1 is mounted over thechip mounting part DP, it is desirable that potential of the chipmounting part DP agrees with a substrate potential of the firstsemiconductor chip SC1. In the case where the first semiconductor chipSC1 is an element for power control, a large difference occurs betweenthe substrate potential of the first semiconductor chip SC1 and asubstrate potential of the second semiconductor chip SC2. For thisreason, if the chip mounting part DP and the second lead terminals LT2are brought close to each other, there arises a possibility that it willbecome impossible to secure insulation between them. In contrast tothis, in the example shown in FIG. 1, a distance w₂ from the second leadterminal LT2 to the chip mounting part DP is larger than a distance w₁from the first lead terminal LT1 to the chip mounting part DP in planeview. For this reason, it is possible to secure insulation between thechip mounting part DP and the second lead terminal LT2.

As shown in FIG. 2, each of the first bonding wire WIR1 and the secondbonding wire WIR2 has an inflection point in a thickness direction ofthe semiconductor device SD.

In addition, in plane view, a distance from the first lead terminals LT1to an inflection point BP₁ of the first bonding wire WIR1 is fartherthan a distance from the first electrode pad PAD11 (or the firstelectrode pad PAD12) of the first semiconductor chip SC1 to theinflection point BP₁. In addition, an angle of the other end of thefirst bonding wire WIR1 (the end coupled to the first lead terminal LT1)the first lead terminal LT1 is smaller than an angle of the one end ofthe first bonding wire WIR1 (the end coupled to the first semiconductorchip SC1) to the first semiconductor chip SC1. This is because the oneend of the first bonding wire WIR1 is coupled to the first electrode padPAD11 (or the first electrode pad PAD12), and subsequently, the otherend of the first bonding wire WIR1 is coupled to the second leadterminal LT2.

In contrast to this, in plane view, a distance from the second leadterminal LT2 to an inflection point BP of the second bonding wire WIR2is shorter than a distance from the second electrode pad PAD2 of thesecond semiconductor chip SC2 to the inflection point BP₂. In addition,an angle of the other end of the second bonding wire WIR2 (the endcoupled to the second lead terminal LT2) to the second lead terminal LT2is larger than an angle of the one end of the second bonding wire WIR2(the end coupled to the second semiconductor chip SC2) to the secondsemiconductor chip SC2. This is because the one end of the secondbonding wire WIR2 is coupled to the second electrode pad PAD2 after theother end of the second bonding wire WIR2 was coupled to the second leadterminal LT2.

Moreover, the semiconductor device SD has a resin holding part PH. Theresin holding part PH is comprised of two adjacent third lead terminalsLT3 and one terminal coupling part LC. The terminal coupling part LCmutually couples ends of the third lead terminal LT3 that are locatedinside the sealing resin MDR. The terminal coupling part LC is formedintegrally with the third lead terminal LT3. In the example shown inFIG. 1, although the third lead terminals LT3 are arranged side by sidewith the second lead terminals LT2, they are not coupled to the bondingwire. Moreover, the bonding wire is also not coupled to the terminalcoupling part LC. Then, the resin holding parts PH are provided on bothsides of the multiple second lead terminals LT2, respectively, in adirection in which the side SID1 extends (an X-direction in FIG. 1). Inother words, the multiple second lead terminals LT2 are provided betweenthe first resin holding part PH and the second resin holding part PH.The resin holding part PH is provided in order to suppress the terminalcoupling part LC from coming off from the sealing resin MDR.

Incidentally, in the example shown in FIG. 1, the number of the secondlead terminals LT2 is fewer than the number of the first lead terminalsLT1. For this reason, the resin holding part PH is arranged side by sidewith the second lead terminals LT2. However, in the case where thenumber of the first lead terminals LT1 is fewer than the number of thesecond lead terminals LT2, the resin holding part PH may be arrangedside by side with the first lead terminals LT1.

The first semiconductor chip SC1 is arranged so as to overlap a centerof the chip mounting part DP. In contrast to this, the secondsemiconductor chip SC2 is smaller than the first semiconductor chip SC1,and for this reason, it is placed approaching toward the side SID1 ofthe chip mounting part DP. In addition, the part of the secondsemiconductor chip SC2 protrudes from the first semiconductor chip SC1in plane view, and this protruded portion overlaps the notch part CPprovided in the chip mounting part DP.

In the example shown in FIG. 1, a width of the notch part CP is madelarger than a width of the second semiconductor chip SC2 in a directionin which the side SID1 extends (the X-direction in FIG. 1). For thisreason, in the X-direction of FIG. 1, the whole of the secondsemiconductor chip SC2 is located inside the notch part CP. However, inthe X-direction of FIG. 1, an end of the second semiconductor chip SC2may overlap the chip mounting part DP.

Moreover, in plane view, a taper is formed in an end TP on the openingside of the notch part CP. This taper faces a direction in which thenotch part CP is increased in width as the position goes outward.Although an angle α of the end TP to the side SID1 (refer to FIG. 3) is,for example, not less than 135° and not more than 180°, it is notlimited to this range.

A width of a side SID2 that faces the notch part CP of the firstsemiconductor chip SC1 is wider than the width of the notch part CP. Forthis reason, in the direction in which the side SID2 extends, both endsof portions of the first semiconductor chip SC1 that are located nearthe side SID2 are supported by the chip mounting part DP. Therefore,stability of the first semiconductor chip SC1 improves as compared withthe case where a width of the chip mounting part DP in a directionperpendicular to the side SID2 is made small. Incidentally, in planeview, a part of the side SID2 overlaps the notch part CP.

The first semiconductor chip SC1 has a semiconductor element and a firstmultilayer wiring layer MINC1 to be described layer) over the firstprincipal plane SFC1. The first electrode pad PAD11 and the firstelectrode pad PAD12 are formed over the first multilayer wiring layerMINC1. In the example shown in FIG. 1, the first electrode pads PAD11are arranged along a fringe of the first semiconductor chip SC1, and thefirst electrode pads PAD12 are arranged more inside of the firstsemiconductor chip SC1 than the first electrode pads PAD11 are. For thisreason, a distance from the first electrode pad PAD12 to the secondsemiconductor chip SC2 is shorter than a distance from the firstelectrode pad PAD11 to the second semiconductor chip SC2. The firstelectrode pad PAD12 is coupled to a power transistor that the firstsemiconductor chip SC1 has; the first electrode pad PAD11 is coupled toeither one of a control circuit or a logic circuit of this powertransistor.

The second semiconductor chip SC2 has a semiconductor element and asecond multilayer wiring layer MINC2 (to be described later) over thethird principal plane SFC3. The second electrode pad PAD2 is formed overthe second multilayer wiring layer MINC2.

Then, as details are shown in FIG. 4, the first semiconductor chip SC1is fixed to the chip mounting part DP with the use of a fixed layer FR1.The chip mounting part DP is a conductive paste material, for example,silver paste, for example.

Moreover, as details are shown in FIG. 1 and FIG. 4, the secondsemiconductor chip is fixed over the first semiconductor chip SC1 withthe use of a fixed layer FR2 in a direction in which the secondmultilayer wiring layer MINC2 faces the first multilayer wiring layerMINC1 of the first semiconductor chip SC1. The fixed layer FR2 isformed, for example, with the use of a non conductive film (NCF). Then,as shown in FIG. 3 and FIG. 4, a part of the fixed layer FR2 creeps up aportion of the side face of the second semiconductor chip SC2 that islocated over the first semiconductor chip SC1 to form a fillet FR21.

Incidentally, the fourth principal plane SFC4 of the secondsemiconductor chip SC2 is covered with a protective layer PR1. In theexample shown in FIG. 4, the protective layer PR1 covers a whole surfaceof the fourth principal plane SFC4. The protective layer PR1 is, forexample, a die attachment film (DAF), and is provided in order toprotect the second semiconductor chip SC2 when the second semiconductorchip SC2 is mounted over the first semiconductor chip SC1. Incidentally,the protective layer PR1 may not be provided.

Moreover, a first inductor IND1 (to be described later) is formed overthe first multilayer wiring layer MINC1 of the first semiconductor chipSC1; the second inductor IND2 is formed over the second multilayerwiring layer MINC2 of the second semiconductor chip SC2. In plane view,the first inductor IND1 and the second inductor IND2 overlap each other,and they are electrically combined mutually (for example, inductivecoupling). Then, a signal for power transistor control that the secondsemiconductor chip SC2 generated is inputted into a circuit for powertransistor control of the first semiconductor chip SC1 through thesecond inductor IND2 and the first inductor IND1.

Furthermore, as shown in FIG. 1 and FIG. 2, the semiconductor device SDhas the sealing resin MDR. The sealing resin MDR seals the followings:the chip mounting part DP; the first semiconductor chip SC1; the secondsemiconductor chip SC2; the first bonding wire WIR1; the second bondingwire WIR2; a coupling part of the first lead terminal LT1 with the firstbonding wire WIR1; a coupling part of the second lead terminal LT2 withthe second bonding wire WIR2; the terminal coupling part LC; a couplingpart of the third lead terminal LT3 with the terminal coupling part LC;and a part of the support part FS2. In the example shown in FIG. 2, theback of the chip mounting part DP is located inside the sealing resinMDR. Incidentally, since FIG. 1 and FIG. 2 show one example of thesealing structure of the semiconductor device SD, the sealing structureof the semiconductor device SD is not limited to the example shown inFIG. 1 and FIG. 2.

FIG. 5 is a plane view showing one example of a structure of the firstsemiconductor chip 501. FIG. 6 is a B-B′ sectional view of FIG. 5. Asshown in FIG. 5, the first semiconductor Chip SC1 has multipletransistors (in the example shown in this figure, a first transistor TR1and two second transistors TR2) as elements for power control. The firsttransistor TR1 is a transistor of a first conductivity type (forexample, p-channel type), and the second transistors TR2 are transistorsof a second conductivity type (for example, an n-channel type). Thefirst transistor TR1 and the two second transistors TR2 are arrangedalong a side of the first semiconductor chip SC1 that is an oppositeside of the side SID2. Then, the first transistor TR1 is located betweenthe two second transistors TR2. Over the first transistor TR1 and thesecond transistors TR2, first electrode pads PAD12 that are coupled tothe respective transistors are formed, respectively.

Moreover, the first semiconductor chip SC1 has at least one firstinductor IND1 (in the example shown in this figure, two inductors). Thefirst inductors IND1 are located in region that overlaps the secondsemiconductor chip SC2 in plane view. As shown in FIG. 6, the firstinductors IND1 are formed with the use of the first multilayer wiringlayer MINC1. In other words, wiring (not illustrated) or via is formedin the same layer as the first inductor IND1. The first multilayerwiring layer MINC1 is formed over a first substrate SUB1. The firstsubstrate SUB1 is a semiconductor substrate such as a silicon substrate,for example. Incidentally, the first transistor TR1 and the secondtransistors TR2 are formed over the first substrate SUB1. Moreover, awinding shaft of the first inductor IND1 faces in a direction thatintersects the first substrate SUB1 (for example, a perpendiculardirection).

Incidentally, as shown in FIG. 5 and FIG. 6, a first depression DEP1 isformed in a region of the first semiconductor chip SC1 that overlaps thesecond semiconductor chip SC2 in plane view. A width of the firstdepression DEP1 is larger than the width of the second semiconductorchip SC2. For this reason, when the first semiconductor chip SC1 and thesecond semiconductor chip SC2 are made to overlap each other, the secondsemiconductor chip SC2 fits into the first depression DEP1.Incidentally, since it is necessary for the part of the secondsemiconductor chip SC2 to protrude from the side SID2 to the outside ofthe first semiconductor chip SC1, the first depression. DEP1 iscontinuous with the side SID2.

The first depression DEP1 is formed by not partially forming at leastone layer of wiring layers (including a layer over which the firstelectrode pad PAD11 and the first electrode pad. PAD12 are formed) thatis located higher above the layer over which the first inductor IND1 isformed in the first multilayer wiring layer MINC1 that the firstsemiconductor chip SC1 has. This shortens a distance between the firstinductor IND1 and a second inductor IND2 described later, and therebyprecision of communication between them can be raised. Incidentally, thefirst semiconductor chip SC1 may not have the first depression DEP1.

FIG. 7 is a plane view showing one example of a structure of the secondsemiconductor chip SC2. FIG. 8 is a C-C′ sectional view of FIG. 7. Thesecond semiconductor chip SC2 has at least one second inductor IND2 (inthe example shown in this figure, two inductors). The number of thesecond inductors IND2 is the same as the number of the first inductorsIND1. When the second semiconductor chip SC2 is arranged over the firstsemiconductor chip SC1, the second inductor IND2 is formed in a positionwhere it overlaps the first inductor IND1. Thereby, the secondsemiconductor chip SC2 is enabled to communicate with the secondsemiconductor chip SC2 through the second inductor IND2 and the firstinductor IND1 in a state were the second semiconductor chip SC2 isisolated from the first semiconductor chip SC1.

As shown in FIG. 8, the second inductor IND2 is formed with the use ofthe second multilayer wiring layer MINC2. The second multilayer wiringlayer MINC2 is formed over a second substrate SUB2. The second substrateSUB2 is a semiconductor substrate such as a silicon substrate, forexample. An element (for example, a MOS transistor) that forms a circuitis formed over the second substrate 2. Moreover, a center axis of thesecond inductor IND2 faces in a direction that intersects the secondsubstrate SUB2 (for example, a perpendicular direction).

Incidentally, as shown in FIG. 7 and FIG. 8, a second depression DEP2 isformed in a region of the second semiconductor chip SC2 that overlapsthe first semiconductor chip SC1 in plane view. The second depressionDEP2 is continuous with three sides of the second semiconductor chip 2.

The second depression DEP2 is formed by not partially forming at leastone layer of wiring layers (including a layer over which the secondelectrode pad PAD2 is formed) that is located higher above the layerover which the second inductor IND2 is formed in the second multilayerwiring layer MINC2 that the second semiconductor chip SC2 has. Thisshortens a distance between the second inductor IND2 and the firstinductor IND1, and thereby the precision of communication between themcan be raised. Incidentally, the second semiconductor chip SC2 may nothave the second depression DEP2.

Moreover, a thickness of the second substrate SUB2 is thicker than thatof the first substrate SUB1. Thereby, the second semiconductor chip SC2is made thicker than the first semiconductor chip SC1. The thickness ofthe second substrate SUB2 is, for example, not less than 300 μm and notmore than 500 μm; a thickness of the first substrate SUB1 is, forexample, not less than 100 μm and not more than 300 μm.

FIG. 9 is a sectional view showing a first example of a shape of thefixed layer FR2. In the example shown in this figure, the fillet FR21 ismade higher than the protective layer PR1 of the second semiconductorchip SC2. Moreover, a part of the fixed layer FR2 protrudes into a sideface of the first semiconductor chip SC1 on a side SID2 side, and formsa fillet FR22. Thus, since the fixed layer FR2 also forms the filletFR22, a fixing strength of the second semiconductor chip SC2 to thefirst semiconductor chip SC1 becomes large. Thereby, as will bedescribed later, in a step of attaching the second bonding wire WIR2 tothe second semiconductor chip SC2, it is possible to suppress the secondsemiconductor chip SC2 from coming off from the first semiconductor chipSC1. Moreover, by the fillets FR21, FR22 being formed, it is possible tosuppress the second semiconductor chip SC2 from bending resulting from astress.

Moreover, it is also possible to suppress a dielectric breakdown fromoccurring between the second semiconductor chip SC2 and the firstsemiconductor chip SC1 in detail, starting point of the dielectricbreakdown between the second semiconductor chip SC2 and the firstsemiconductor chip SC1 is a portion of the second semiconductor chip SC2where its distance to the first semiconductor chip SC1 is short. In thisembodiment, a portion of the side face of the second semiconductor chipSC2 that is located over the first semiconductor chip SC1 is coveredwith the fillet FR21. For this reason, it is possible to suppress thedielectric breakdown from occurring between the first semiconductor chipSC1 and the second semiconductor chip SC2 with the side face of thesecond semiconductor chip SC2 acting as a starting point.

FIG. 10 is a sectional view showing a second example of the shape of thefixed layer FR2. The example shown in this figure is the same as theexample shown in FIG. 9 except for point that the fillet FR21 does notreach the protective layer PR1.

FIG. 11 is a sectional view showing a third example of the shape of thefixed layer FR2. Although in the example shown in this figure, a part ofthe fillet FR21 is made higher than the protective layer PR1, it is thesame as the example shown in FIG. 9 except for a point that a remainingportion of the fillet FR21 does not reach the protective layer PR1.

Each figure of FIG. 12 to FIG. 15 is a sectional view for explaining amethod for manufacturing a semiconductor device SD. First, the firstsemiconductor chip SC1 and the second semiconductor chip SC2 aremanufactured. The first semiconductor chip SC1 and the secondsemiconductor chip SC2 are manufactured as follows, for example.

First, an element isolation film is formed over the first substrate SUB1(or the second substrate SUB2) that is in a wafer state. Thereby, anelement formation region is isolated. The element isolation film isformed, for example, by using an STI method, but may be formed by usinga LOCOS method. Next, a gate insulating film and a gate electrode areformed over the semiconductor substrate located in the element formationregion. The gate insulating film may be a silicon oxide film, or may bea high dielectric constant film (for example, hafnium silicate film)whose permittivity is higher than that of the silicon oxide film. In thecase where the gate insulating film is the silicon oxide film, the gateelectrode is formed with a polysilicon film. Moreover, in the case wherethe gate insulating film is the high dielectric constant film, the gateelectrode is formed with a laminated film of a metallic film (forexample, TiN) and the polysilicon film. Moreover, when the gateelectrode is formed with polysilicon, in a step of forming the gateelectrode, polysilicon resistance may be formed over the elementisolation film.

Next, an extension region of a source and a drain is formed over thesemiconductor substrate that is located in the element formation region.Next, sidewalls are formed over side walls of the gate electrode. Next,an impurity region that becomes a source and a drain is formed in thesemiconductor substrate located in the element formation region. Thus, aMOS transistor is formed over the semiconductor substrate.

Moreover, in a manufacturing step of the first semiconductor chip thefirst transistor TR1 and the second transistors TR2 are formed by usingat least a part of the above-mentioned step.

Next, the first multilayer wiring layer MINC1 (or the second multilayerwiring layer MINC2) is formed over the element isolation film and theMOS transistor. The first electrode pads PAD11, PAD12 (or the secondelectrode pad PAD2) are formed over a wiring layer of an uppermostlayer. Next, a protective insulation film (a passivation film) is formedover the multilayer wiring layer. An aperture located above theelectrode pad is formed in the protective insulation film.

After this, the first semiconductor chip SC1 is formed by dicing thewafer that becomes the first semiconductor chips SC1 into individualchips.

Moreover, regarding the wafer that becomes the second semiconductorchips SC2, as shown in FIG. 12A, the protective layer PR1 is stuck downon a plane that serves as the fourth principal plane SFC4 of the secondsemiconductor chip SC2 in the wafer. Moreover, a bump BMP is formed oneach of the second electrode pads PAD2. The bump BMP is formed with theuse of a metal that easily join the second bonding wire WIR2 such asgold, for example.

Next, as shown in FIG. 12B, a wafer that becomes the secondsemiconductor chips SC2 is diced into individual chips together with theprotective layer PR1. Thereby, the second semiconductor chip SC2 ismanufactured with the protective layer PR1 provided over it.

Incidentally, before dicing the wafer into the first semiconductor chipsSC1, the first substrate SUB1 of the first semiconductor chips SC1 isground to be thinned. Similarly, before providing the protective layerPR1 over the second semiconductor chip SC2, the second substrate SUB2 ofthe second semiconductor chips SC2 is ground to be thinned, if needed.

Next, as shown in FIG. 13A, the fixed layer FR2 is provided over aregion of the first principal plane SFC1 of the first semiconductor chipSC1 over which the second semiconductor chip SC2 is mounted. Next, asshown in FIG. 13B, the second semiconductor chip SC2 is mounted over thefirst semiconductor chip SC1. At this time, the third principal planeSFC3 of the second semiconductor chip SC is made to face the fixed layerFR2. Moreover, the bump BMP of the second semiconductor chip SC2 is madenot to be covered with the first semiconductor chip SC1 or the fixedlayer FR2 at this time.

Next, as shown in FIG. 14A, a laminated body of the first semiconductorchip SC1 and the second semiconductor chip SC2 is mounted over the chipmounting part DP of the lead frame with the use of the fixed layer FR1.At this time, the notch part CP of the chip mounting part. DP and thehump BMP of the second semiconductor chip SC2 are made to overlap eachother.

Next, as shown in FIG. 14B, the first electrode pads PAD11 and the firstelectrode pads PAD12 of the first semiconductor chip SC1 are coupled tothe first lead terminals LT1 by using the first bonding wires WIR1. Atthis time, after one end of the first bonding wire WIR1 was fixed to thefirst electrode pad PAD11 (or the first electrode pad PAD12), the otherend of the first bonding wire WIR1 is fixed to the first lead terminalLT1.

Then, as shown in FIG. 14C, the lead frame is turned upside down.

Next, as shown in FIG. 15A, the second electrode pad PAD2 of the secondsemiconductor chip SC2 is coupled to the second lead terminal LT2 byusing the second bonding wire WIR2. At this time, after the other end ofthe second bonding wire WIR2 was fixed to the second lead terminal LT2,the one end of the second bonding wire WIR2 is fixed to the bump BMP(namely, the second electrode pad PAD2). Incidentally, in order toperform this step, it is necessary to provide the same notch as thenotch part. CP also in a stage for holding the lead frame.

In this step, the bump BMP is formed in advance over the secondelectrode pad PAD2. For this reason, the one end of the second bondingwire WIR2 can be coupled to the second electrode pad PAD2 withoutpressing the one end of the second bonding wire WIR2 to the secondelectrode pad PAD2 firmly. Therefore, when the second bonding wire WIR2is fixed to the second electrode pad PAD2, it is possible to suppressthe second semiconductor chip SC2 from coming off from the firstsemiconductor chip SC1.

Moreover, when the other end of the second bonding wire WIR2 is attachedto the second lead terminal LT2 after the one end of the second bondingwire WIR2 was attached to the second electrode pad PAD2, during a timewhen the other end of the second bonding wire WIR2 is attached to theysecond lead terminal LT2 after the one end of the second bonding wireWIR2 was attached to the second electrode pad PAD2, there arises apossibility that a force is added to the second semiconductor chip SC2through the second bonding wire WIR2. In this case, there arises apossibility that the second semiconductor chip SC2 will come off fromthe first semiconductor chip SC1. In this embodiment, since the secondbonding wire WIR2 is attached to the second electrode pad PAD2 after itwas attached to the second lead terminals LT2, it is possible tosuppress such a problem from occurring.

Moreover, the second semiconductor chip SC2 is made thicker than thefirst semiconductor chip SC1. Therefore, when the second bonding wireWIR2 is attached to the second semiconductor chip SC2, it is possible tosuppress the second semiconductor chip SC2 from being damaged.

Then, as shown in FIG. 155, the lead frame is turned upside down.Thereby, conveyance of the lead frame becomes easy. Next, the sealingresin MDR is formed by using a metallic mold for sealing.

Next, as shown in FIG. 15C, portions of the first lead terminal LT1 andthe second lead terminal LT2 that are located outside the sealing resinMDR are deformed to be made as terminals.

Incidentally, the second semiconductor chip SC2 may be mounted over thefirst semiconductor chip SC1 after mounting the first semiconductor chipSC1 over the chip mounting part DP.

FIG. 16 and FIG. 17 are flowcharts showing details of the step shown inFIGS. 13A and 13B. First, as shown in FIG. 16A, a sheet-like fixed layerFR2 cut into a predetermined shape is held (for example, being adsorbed)by using the assembly apparatus AT. In this state, a cover film CF isprovided on a plane of the fixed layer FR2 that is held by the assemblyapparatus AT. Next, by using the assembly apparatus AT, the fixed layerFR2 is pressed to a region of the first semiconductor chip SC1 overwhich the second semiconductor chip SC2 is mounted.

Next, as shown in FIG. 16B, the assembly apparatus AT is elevated withthe cover film CF adsorbed thereto. Thereby, the cover film CF isremoved from the fixed layer FR2.

Next, as shown in FIG. 17A, the assembly apparatus AT is made to holdthe second semiconductor chip SC2. The assembly apparatus AT adsorbs,for example, the fourth principal plane SFC4 of the second semiconductorchip SC2. Since the fourth principal plane SFC is covered with theprotective layer PR1 at this time, no flaw is given to the fourthprincipal plane SFC4.

Next, the second semiconductor chip SC2 is pressed to the fixed layerFR2 using the assembly apparatus AT. Thereby, the second semiconductorchip SC2 is fixed over the first semiconductor chip SC1. Moreover, thefillets FR21, FR22 are formed in the fixed layer FR2 at this time.

Then, as shown in FIG. 17B, the second semiconductor chip SC2 isdetached from the assembly apparatus AT.

Next, an effect of this embodiment will be explained. The notch part CPis formed in the chip mounting part DP in this embodiment. Then, inplane view, the second electrode pad PAD2 of the second semiconductorchip SC2 overlaps the notch part CP. Therefore, when attaching the oneend of the second bonding wire WIR2 to the second electrode pad PAD2, itis possible to suppress a bonding tool and the chip mounting part DPfrom interfering each other.

Moreover, second bonding wires WIR21 located at ends among multiplesecond bonding wires WIR2 (for example, the second bonding wire WIR2located at a right end and the second bonding wire WIR2 located at aleft end in FIG. 3) extend aslant to the side SID1 of the chip mountingpart DP. For this reason, there arises a possibility that the secondbonding wire WIR21 or the bonding tool for attaching this wire willcontact with the end TP of the notch part CP. In contrast to this, inthis embodiment, a taper is provided at the end TP of the notch part CP.Therefore, it is possible to suppress the second bonding wire WIR21 orthe bonding tool for attaching this wire from contacting with the end TPof the notch part CP.

Modification

FIG. 18 is a plane view of a first semiconductor chip SC1 according to amodification, and FIG. 19 is a plane view of a second semiconductor chipSC2 according to the modification. The semiconductor device SD accordingto this modification has the same configuration as that of thesemiconductor device SD according to the embodiment except for pointsthat a protrusion PTN1 is formed over the first principal plane SFC1 ofthe first semiconductor chip SC1 and that a depression PTN2 is formedover the second principal plane SFC2 of the second semiconductor chipSC2.

The protrusion PTN1 is formed with the use of the first multilayerwiring layer MINC1 of the first semiconductor chip SC1 or the protectiveinsulation film over it; the depression PTN2 is formed with the use ofthe second multilayer wiring layer MINC2 of the second semiconductorchip SC2 or the protective insulation film over it. Specifically, theprotrusion PTN1 is formed by removing a portion located in acircumference of the protrusion PTN1 over at least one layer of theuppermost layers of the first semiconductor chip SC1. Moreover, thedepression PTN2 is formed by removing a region that will serve as thedepression PTN2 in at least the one layer of the uppermost layers of thefirst semiconductor chip SC1.

A planar shape of the depression PTN2 is the same as a planar shape ofthe protrusion PTN1. Then, in a state where the first semiconductor chipSC1 and the second semiconductor chip SC2 are made to overlap eachother, the protrusion PTN1 overlaps the depression PTN2. At least anupper part of the protrusion PTN1 may fit into the depression PTN2.

Also with this modification, the same effect as that of the embodimentcan be acquired. Moreover, precision of relative positions of the firstsemiconductor chip SC1 and the second semiconductor chip SC2 can beraised by overlapping positions of the protrusion PTN1 and thedepression PTN2. By this, it is possible to suppress communication errorfrom occurring between the first inductor IND1 and the second inductorIND2. Especially, in the case where at least the upper part of theprotrusion PTN1 is made to fit into the depression PTN2, precision ofthe relative positions of the first semiconductor chip SC1 and thesecond semiconductor chip SC2 becomes especially high.

Incidentally, even in the case where the depression is formed in thefirst principal plane SFC1 of the first semiconductor chip SC1 and theprotrusion is formed in the third principal plane SFC3 of the secondsemiconductor chip SC2, the same effect as that of this modification canbe acquired.

In the foregoing, although the invention made by the present inventorswas concretely explained based on the embodiments, it goes withoutsaying that the present invention is not limited to the embodiments, andcan be modified variously in a range that does not deviate from itsgist.

What is claimed is:
 1. A semiconductor device, comprising: a chipmounting part; a first semiconductor chip that has a first principalplane and a second principal plane being an opposite side plane to thefirst principal plane and is mounted over the chip mounting part in adirection in which the second principal plane faces the chip mountingpart; and a second semiconductor chip that has a third principal planeand a fourth principal plane being an opposite side plane to the thirdprincipal plane and a part of which is mounted over the firstsemiconductor chip in a direction in which the third principal planefaces the first principal plane, wherein in plane view, the chipmounting part has a notch part and a part of the second semiconductorchip overlaps the notch part, and further wherein the semiconductordevice comprises: an electrode pad located in a region of the thirdprincipal plane of the second semiconductor chip that overlaps the notchpart; and a bonding wire whose one end couples to the electrode pad. 2.The semiconductor device according to claim 1, comprising; a firstinductor formed over the first principal plane of the firstsemiconductor chip; and a second inductor formed over the thirdprincipal plane of the second semiconductor chip, wherein in plane view,the first inductor and the second inductor overlap each other.
 3. Thesemiconductor device according to claim 1, wherein a width of a side ofthe first semiconductor chip that faces the notch part is wider than awidth of the notch part, and wherein in plane view, a part of the firstsemiconductor chip overlaps the notch part.
 4. The semiconductor deviceaccording to claim 1, wherein in plane view, a taper is formed in an endon an opening side of the notch part.
 5. The semiconductor deviceaccording to claim 1, comprising: a first lead terminal to which theother end of the bonding wire couples; two second lead terminalsarranged side by side with the first lead terminal; a terminal couplingpart that couples mutually ends on the chip mounting part side of thetwo second lead terminals; and a sealing resin that seals thefollowings: the chip mounting part; the first semiconductor chip; thesecond semiconductor chip; the bonding wire; a portion of the first leadterminal to which at least the bonding wire couples; a portion of thetwo second terminals to which at least the terminal coupling partcouples; and the terminal coupling part.
 6. The semiconductor deviceaccording to claim 5, comprising: a plurality of sets each comprised ofthe two second lead terminals and the terminal coupling part; and havinga plurality of the first lead terminals between the first set and thesecond set.
 7. The semiconductor device according to claim 5, wherein anangle of the other end of the bonding wire to the first lead terminal islarger than an angle of the one end of the bonding wire to the secondsemiconductor chip.
 8. The semiconductor device according to claim 1,wherein the second semiconductor chip is thicker than the firstsemiconductor chip.
 9. The semiconductor device according to claim 1,comprising: a protective layer provided over the fourth principal planeof the second semiconductor chip.
 10. The semiconductor device accordingto claim 1, comprising: a power controller element formed over the firstsemiconductor chip.
 11. The semiconductor device according to claim 1,comprising: a fixed layer located between the third principal plane ofthe second semiconductor chip and the first principal plane of the firstsemiconductor chip, wherein one part of the fixed layer is located overa side face of the second semiconductor chip and the other part of thefixed layer is located over a region of a side face of the firstsemiconductor chip that overlaps the second semiconductor chip.
 12. Thesemiconductor device according to claim 1, comprising: a protrusionformed in either one of the first principal plane of the firstsemiconductor chip and the third principal plane of the secondsemiconductor chip; and an another notch part formed in the other of thefirst principal plane of the first semiconductor chip and the thirdprincipal plane of the second semiconductor chip, wherein in plane view,an outer shape of the protrusion and an outer shape of the other notchpart have the same shape and the protrusion and the other notch partoverlap each other.
 13. The semiconductor device according to claim 1,wherein the notch is formed at a peripheral edge of the chip mountingpart.